1. Field of the Invention
The present invention relates to CMOS integrated circuits and more particularly to a protective circuit for preventing latch-up of the parasitic thyristor which exists in the CMOS integrated structure.
2. Description of the Prior Art
It is well known that the conventional CMOS circuit comprises a P channel MOS transistor and an N channel MOS transistor formed on the surface of a semiconductor substrate. It is also well known that due to the positioning and interconnection of the various regions on the substrate, a parasitic thyristor structure inevitably exists. The parasitic thyristor is formed in such a way that when triggered, such as by power supply transients, the parasitic thyristor is connected as a substantial short circuit across the power supply. As a result, if the parasitic thyristor is triggered and latches on, substantial, usually destructive, currents flow from the power supply through the MOS integrated circuit. As an example, the large current can substantially increase the power dissipated in the MOS circuit, overheating and ultimately destroying the circuit. As integration circuit densities of CMOS circuits increase, the latch-up phenomenon associated with parasitic thyristors becomes more serious, resulting in a decrease in the reliability of the circuit and a practical limitation in the integration density.
The latch-up problem will be better appreciated with reference to FIG. 1 which is a diagram showing the structure of a conventional and typical CMOS (complementary MOS) circuit. As shown in FIG. 1, a CMOS circuit 10 comprises a P channel MOS region 10a and an N channel MOS region 10b, formed in predetermined regions of an N type semiconductor substrate 11.
The P channel MOS transistor 10a comprises a P type impurity diffusion region (a source region) 12 and a P type impurity diffusion region 13 (a drain), each formed in a predetermined region on the surface of the semiconductor substrate 11. A gate electrode 14 is formed over the surface of the semiconductor substrate 11 between the P type impurity diffusion regions 12 and 13, and an insulating film (not shown) is interposed therebetween.
On the other hand, the N channel MOS transistor is formed in a P type well 21 formed on the surface of the N type semiconductor substrate 11. More specifically, the N channel MOS transistor 10b comprises an N type impurity diffusion region (a drain) 22 and an N type impurity diffusion region 23 (a source) each diffused into the P type well 21. A gate electrode 24 is formed over the surface of the P type well 21 between the N type impurity diffusion regions 22 and 23, and an insulating film (not shown) is interposed therebetween.
The P channel MOS transistor region is provided with an N type impurity diffusion region 15 for providing electrical connection to the N type semiconductor substrate 11. In addition, a P type impurity diffusion region 25 for providing electrical contact to the P type well 21 is provided in the P type well 21. The N type impurity diffusion region 15 and the P type impurity diffusion region 25 for providing electrical connection to the substrate 11 and the well 21 provide substrate bias, respectively, so that the potentials on the substrate and the well are stabilized.
The illustrated CMOS circuit, and typically a plurality of such CMOS circuits arranged to perform a complex function, are provided with connection means 16, 26 for connecting the circuit to a power supply. It is seen that the connection terminal 16 is arranged for connection to the positive terminal of a power supply V.sub.cc, and the thus supplied positive voltage is connected to both the N type impurity diffusion region 15 and P type impurity diffusion region 12. Similarly, the negative terminal of the power supply is connected to ground interconnect terminal 26 (GND) which in turn is connected to the N type impurity diffusion region 23 and the P type impurity diffusion region 25 of the N channel MOS transistor. Also as illustrated in FIG. 1, the semiconductor substrate 11 has a substrate distributed resistance shown as resistor 17 and the P type well also has a distributed resistance shown as resistor 27.
As will be appreciated by those familiar with CMOS circuitry, the conventional CMOS circuit illustrated in FIG. 1, including the N channel transistor and P channel transistor formed on the surface of the semiconductor substrate, has an inherent parasitic thyristor which, when triggered, provides a connection across the power supply terminals Vcc and GND. FIG. 2 is a diagram showing an equivalent circuit of the parasitic thyristor formed in the CMOS circuit of FIG. 1. In FIG. 2, the parasitic thyristor comprises cross-coupled bipolar transistors 30, 31.
The PNP parasitic bipolar transistor 30 includes an emitter, the P type impurity diffusion source region 12; a base, the N type substrate 11; and a collector, the P type material of the well 21. The NPN parasitic bipolar transistor includes a collector, the N type substrate 11; a base, the P type well 21; and an emitter, the N type impurity diffusion drain region 23. Because the N channel substrate and P well 21 are common to both of the parasitic transistors, the base to collector connections illustrated in FIG. 2 are inherently present. Furthermore, the base to emitter resistances 17 and 27 of FIG. 2 are provided by the substrate resistances 17, 27 described in connection with FIG. 1.
The parasitic bipolar transistors 30, 31, and thus the parasitic thyristors formed by cross coupling those transistors are generally biased to be rendered non-conductive. However, if current laterally flows in the semiconductor substrate 11 and the P type well 21, a potential difference is formed across each of the resistances 17 and 27. As a result, the parasitic transistors 30 and 31 are provided with base current and thus begin to conduct.
It will be appreciated that if conduction increases to a predetermined level, the cross coupling of the transistors will cause the parasitic thyristor to latch on, imposing a connection across the power supply terminals 16, 26 which is substantially a short circuit.
The manner in which latch-up occurs will now be described. As shown in FIG. 2, terminal 16 is normally connected to the positive terminal of the power supply V.sub.cc (typically 5 volts) and the terminal 26 to the negative terminal of the power supply, typically referred to as ground GND. Whenever current is flowing laterally in the semiconductor substrate and P type well 21, there will be a voltage drop across resistances 17 and 27. Since the resistance 17 is connected between the emitter 12 and base 11 of the PNP transistor 30, the potential of the base 11 will decrease with respect to that of the emitter 12. Thus, the PNP transistor 30 will begin to turn on, allowing current flow from emitter 12 to collector 21, raising the voltage at the base 21 of the NPN transistor 31. Thus, since the emitter of the transistor 31 is grounded, the transistor 31 also begins to turn on, so that current flow which had initiated at the V.sub.cc terminal is returned to the ground terminal 26. As a result, the voltage drop across the resistance 17 is further increased, further increasing the base drive to PNP transistor 30 so that the transistor 30 turns on deeper. As a result, a higher voltage is applied to the base of the NPN transistor 31, so that the transistor 31 is also turned on more deeply. As a result, current flows from the positive power supply terminal V.sub.cc through the parasitic transistors 30, 31 (which as noted above are cross coupled to form a parasitic thyristor) to the ground terminal GND. This conductive state of the parasitic transistors is referred to as latch-up of the parasitic thyristor, and as will now be apparent produces substantial power consumption in the CMOS circuit. As a result, the CMOS circuit may be destroyed by heat generated due to the power dissipated in the parasitic thyristor.
Steps have been taken in the prior art in order to prevent or minimize the possibility of such a latch-up phenomenon. Those approaches have included:
(1) An N+ impurity diffusion region or a P+ impurity diffusion region (a guard band) is provided between the N channel transistor region and the P channel transistor region so that the well potential is stabilized (the potential gradient in the well region is removed) and the minority carriers are absorbed in the above described region to reduce the lifetime of the minority carriers, whereby latch-up immunity is increased.
(2) Impurities or neutrons are implanted into the semiconductor substrate and the well region so that the current gain of each of the transistors 30 and 31 of the parasitic thyristors is decreased, whereby current flowing through the parasitic transistors is reduced.
(3) The P type well is deep formed or an impurity concentration in the P type well region is increased so that resistance of the well region is reduced, whereby the well potential is stabilized.
In addition to the above described approaches, an approach of providing voltage drop means between the power-supply voltage V.sub.cc and the source region of the parasitic bipolar transistor has been considered, which is disclosed in, for example, Japanese Patent Laying-Open Gazette No. 130557/1983.
The foregoing approaches used to prevent or minimize latch-up in a CMOS circuit have a number of disadvantages. With respect to those which alter the semiconductor structure itself, such as the first three listed above, typically the approach has complicated the manufacturing process, such as by requiring additional steps for implantation of impurities or provision of a guard band. The added structure also tends to reduce the integration density which would otherwise be possible. Integration density is decreased not only for allowing the inclusion of additional structure such as guardbands, but also in providing sufficient distance between the various regions of the integrated circuit since very tight packing aggravates the parasitic thyristor latch-up problem. The power supply limiting approach also has its disadvantages in requiring a normally unwanted voltage drop between the power supply and the CMOS circuit, in the ability to reliably prevent latch-up under all conditions, and, in some cases, in the reproducibility of the voltage drop needed to prevent latch-up.
Nor has it been possible to alleviate the problem of latch-up in a CMOS circuit by appropriate power supply design, such as by incorporation of a current foldback circuit. Most significantly, the response time of known current foldback circuits is not sufficient to prevent latch-up, and furthermore the current foldback circuits are complicated and impractical to integrate on-chip, and are therefore not suitable for a CMOS integrated circuit.